A reference voltage at half-VDD is not sufficient enough to provide fast sensing and does not allow operating with a shorter cycle time. Fast sensing can be performed only if there is a large drain source voltage (Vds) for transistors in sense amplifier. The solution is to use VSS- or VDD-sensing, dependent on the type of memory cell access transistor. For n-type access device VSS-sensing is used. To implement VSS-sensing, a stable reference level close to VSS is required. There are two conventional ways of generating the reference level: using an analog regulator or using reference cells. Each method has its own advantages and drawbacks.
Analog push-pull voltage regulator requires relatively small area for generator. However, large voltage regulation (dV/dI) requires a large reservoir capacitor to compensate for the ripple of the reference level. The ripple of reference level can be minimized by improving the response of the analog regulator, but it can be essentially done only by increasing standby current. Another problem for analog regulator is to generate stable levels close to VSS.
For conventional sensing schemes with reference cells, additional area in the array is needed and reference cells are usually different from regular memory cells and thus more complicated. To activate reference cells, special levels different from the power supply voltage (>VDD) and the ground voltage (<VSS) are required. Usually these levels are the same as the levels for regular word-lines. This increases load for internal generators that usually have low efficiency, and hence results in higher power consumption.
Accordingly, new schemes and methods are desired for the generation of a precise reference voltage level for eDRAM.